module vct_dda_6662 (Z, X, Y);
	
	input [5:0] Y;
	input [5:0] X;
	output [5:0] Z;
	
	wire [7:0] S;
	wire [7:0] C;
	wire [6:0] carry;
	
	// generate the partial products.
	wire N0_0_4;
	and pp1(N0_0_4, X[4], Y[0]);
	wire N0_0_5;
	and pp2(N0_0_5, X[5], Y[0]);
	wire N0_1_4;
	and pp3(N0_1_4, X[3], Y[1]);
	wire N0_1_5;
	and pp4(N0_1_5, X[4], Y[1]);
	wire N0_1_6;
	and pp5(N0_1_6, X[5], Y[1]);
	wire N0_2_4;
	and pp6(N0_2_4, X[2], Y[2]);
	wire N0_2_5;
	and pp7(N0_2_5, X[3], Y[2]);
	wire N0_2_6;
	and pp8(N0_2_6, X[4], Y[2]);
	wire N0_2_7;
	and pp9(N0_2_7, X[5], Y[2]);
	wire N0_3_4;
	and pp10(N0_3_4, X[1], Y[3]);
	wire N0_3_5;
	and pp11(N0_3_5, X[2], Y[3]);
	wire N0_3_6;
	and pp12(N0_3_6, X[3], Y[3]);
	wire N0_3_7;
	and pp13(N0_3_7, X[4], Y[3]);
	wire N0_3_8;
	and pp14(N0_3_8, X[5], Y[3]);
	wire N0_4_4;
	and pp15(N0_4_4, X[0], Y[4]);
	wire N0_4_5;
	and pp16(N0_4_5, X[1], Y[4]);
	wire N0_4_6;
	and pp17(N0_4_6, X[2], Y[4]);
	wire N0_4_7;
	and pp18(N0_4_7, X[3], Y[4]);
	wire N0_4_8;
	and pp19(N0_4_8, X[4], Y[4]);
	wire N0_4_9;
	and pp20(N0_4_9, X[5], Y[4]);
	wire N0_5_5;
	and pp21(N0_5_5, X[0], Y[5]);
	wire N0_5_6;
	and pp22(N0_5_6, X[1], Y[5]);
	wire N0_5_7;
	and pp23(N0_5_7, X[2], Y[5]);
	wire N0_5_8;
	and pp24(N0_5_8, X[3], Y[5]);
	wire N0_5_9;
	and pp25(N0_5_9, X[4], Y[5]);
	wire N0_5_10;
	and pp26(N0_5_10, X[5], Y[5]);
	wire N0_5_4;
	and pp27(N0_5_4, X[2], Y[1]);
	wire N0_6_4;
	and pp28(N0_6_4, X[1], Y[2]);
	wire N0_7_4;
	and pp29(N0_7_4, X[0], Y[3]);

	// PP Reduction
	// Elements from matrix 0 
	// Elements from matrix 1 
	// In matrix 1 adding FA to column 4 
	wire N2_0_4;
	wire N2_1_5;
	full_adder FA1(N2_1_5, N2_0_4, N0_0_4, N0_1_4, N0_2_4);
	// In matrix 1 adding HA to column 4 
	wire N2_2_4;
	wire N2_3_5;
	half_adder HA1(N2_3_5, N2_2_4, N0_3_4, N0_4_4);
	// In matrix 1 adding FA to column 5 
	wire N2_0_5;
	wire N2_1_6;
	full_adder FA2(N2_1_6, N2_0_5, N0_0_5, N0_1_5, N0_2_5);
	// Elements from matrix 2 
	// In matrix 2 adding FA to column 4 
	wire N3_0_4;
	wire N3_1_5;
	full_adder FA3(N3_1_5, N3_0_4, N0_5_4, N0_6_4, N0_7_4);
	// In matrix 2 adding FA to column 5 
	wire N3_0_5;
	wire N3_1_6;
	full_adder FA4(N3_1_6, N3_0_5, N0_3_5, N0_4_5, N0_5_5);
	// In matrix 2 adding HA to column 5 
	wire N3_2_5;
	wire N3_3_6;
	half_adder HA2(N3_3_6, N3_2_5, N2_0_5, N2_1_5);
	// In matrix 2 adding FA to column 6 
	wire N3_0_6;
	wire N3_1_7;
	full_adder FA5(N3_1_7, N3_0_6, N0_1_6, N0_2_6, N0_3_6);
	// In matrix 2 adding FA to column 6 
	wire N3_2_6;
	wire N3_3_7;
	full_adder FA6(N3_3_7, N3_2_6, N0_4_6, N0_5_6, N2_1_6);
	// In matrix 2 adding FA to column 7 
	wire N3_0_7;
	wire N3_1_8;
	full_adder FA7(N3_1_8, N3_0_7, N0_2_7, N0_3_7, N0_4_7);
	// Elements from matrix 3 
	// In matrix 3 adding HA to column 4 
	wire N4_0_4;
	wire N4_1_5;
	assign N4_1_5 = N2_0_4;
	assign N4_0_4 = !N2_0_4;
	// In matrix 3 adding FA to column 5 
	wire N4_0_5;
	wire N4_1_6;
	full_adder FA8(N4_1_6, N4_0_5, N2_3_5, N3_0_5, N3_1_5);
	// In matrix 3 adding FA to column 6 
	wire N4_0_6;
	wire N4_1_7;
	full_adder FA9(N4_1_7, N4_0_6, N3_0_6, N3_1_6, N3_2_6);
	// In matrix 3 adding FA to column 7 
	wire N4_0_7;
	wire N4_1_8;
	full_adder FA10(N4_1_8, N4_0_7, N0_5_7, N3_0_7, N3_1_7);
	// In matrix 3 adding FA to column 8 
	wire N4_0_8;
	wire N4_1_9;
	full_adder FA11(N4_1_9, N4_0_8, N0_3_8, N0_4_8, N0_5_8);
	// Elements from matrix 4 
	// In matrix 4 adding HA to column 4 
	wire N5_0_4;
	wire N5_1_5;
	half_adder HA3(N5_1_5, N5_0_4, N2_2_4, N3_0_4);
	// In matrix 4 adding FA to column 5 
	wire N5_0_5;
	wire N5_1_6;
	full_adder FA12(N5_1_6, N5_0_5, N3_2_5, N4_0_5, N4_1_5);
	// In matrix 4 adding FA to column 6 
	wire N5_0_6;
	wire N5_1_7;
	full_adder FA13(N5_1_7, N5_0_6, N3_3_6, N4_0_6, N4_1_6);
	// In matrix 4 adding FA to column 7 
	wire N5_0_7;
	wire N5_1_8;
	full_adder FA14(N5_1_8, N5_0_7, N3_3_7, N4_0_7, N4_1_7);
	// In matrix 4 adding FA to column 8 
	wire N5_0_8;
	wire N5_1_9;
	full_adder FA15(N5_1_9, N5_0_8, N3_1_8, N4_0_8, N4_1_8);
	// In matrix 4 adding FA to column 9 
	wire N5_0_9;
	wire N5_1_10;
	full_adder FA16(N5_1_10, N5_0_9, N0_4_9, N0_5_9, N4_1_9);

	buf bufC0(C[0], N4_0_4);
	buf bufC1(C[1], N5_0_5);
	buf bufC2(C[2], N5_0_6);
	buf bufC3(C[3], N5_0_7);
	buf bufC4(C[4], N5_0_8);
	buf bufC5(C[5], N5_0_9);
	buf bufC6(C[6], N0_5_10);
	buf bufS0(S[0], N5_0_4);
	buf bufS1(S[1], N5_1_5);
	buf bufS2(S[2], N5_1_6);
	buf bufS3(S[3], N5_1_7);
	buf bufS4(S[4], N5_1_8);
	buf bufS5(S[5], N5_1_9);
	buf bufS6(S[6], N5_1_10);

	and CPA1(carry[0],C[0],S[0]);
	reduced_full_adder CPA2(carry[1],carry[0],C[1],S[1]);
	full_adder CPA3(carry[2],Z[0],carry[1],C[2],S[2]);
	full_adder CPA4(carry[3],Z[1],carry[2],C[3],S[3]);
	full_adder CPA5(carry[4],Z[2],carry[3],C[4],S[4]);
	full_adder CPA6(carry[5],Z[3],carry[4],C[5],S[5]);
	full_adder CPA7(Z[5],Z[4],carry[5],C[6],S[6]);
endmodule
